An On-line Diagnostic Method for Open-circuit Switch Faults in NPC Multilevel Converters

On-line condition monitoring is of paramount importance for multilevel converters used in safety-critical applications. A novel on-line diagnostic method for detecting open-circuit switch faults in neutral-point-clamped (NPC) multilevel converters is introduced in this paper. The principle of this method is based on monitoring the abnormal variation of the dc-bus neutral-point current in combination with the existing information on instantaneous switching states and phase currents. Advantages of this method include simpler implementation and faster detection speed compared to other existing diagnostic methods in the literature. In this method, only one additional current sensor is required for measuring the dc-bus neutral-point current, therefore the implementation cost is low. Simulation and experimental results based on a lab-scale 50 kVA adjustable speed drive (ASD) with a three-level NPC inverter validate the efficacy of this novel diagnostic method

An Advanced Three-Level Active Neutral-Point-Clamped Converter With Improved Fault-Tolerant Capabilities

A resilient fault-tolerant silicon carbide (SiC) three-level power converter topology is introduced based on the traditional active neutral-point-clamped converter. This novel converter topology incorporates a redundant leg to provide fault tolerance during switch open-circuit faults and short-circuit faults. Additionally, the topology is capable of maintaining full output voltage and maximum modulation index in the presence of switch open and short-circuit faults. Moreover, the redundant leg can be employed to share load current with other phase legs to balance thermal stress among semiconductor switches during normal operation. A 25-kW prototype of the novel topology was designed and constructed utilizing 1.2-kV SiC metal-oxide-semiconductor field-effect transistors. Experimental results confirm the anticipated theoretical capabilities of this new three-level converter topology

Investigation of Fault-Tolerant Capabilities in an Advanced Three-Level Active T-Type Converter

A novel fault-tolerant three-level power converter topology, named advanced three-level active T-Type (A3L-ATT) converter, is introduced to increase the reliability of multilevel power converters used in safety-critical applications. This new fault-tolerant multilevel power converter is derived from the conventional T-Type converter topology. The topology has significantly improved the fault-tolerant capability under any open circuit or certain short-circuit faults in the semiconductor devices. In addition, under healthy condition, the redundant phase leg can be utilized to share overload current with other main legs, which enhances the overload capability of the converter. The conduction losses in the original outer devices can be reduced by sharing the load current with the redundant leg. Moreover, unlike other existing fault-tolerant power converters in the literature, full output voltages can be always obtained in this proposed A3L-ATT converter during fault-tolerant operation. A 13.5-kW ATT-A3L converter prototype was developed and constructed using silicon carbide MOSFETs. Simulation and experimental results were obtained to substantiate the theoretical claims of this new fault-tolerant power converter

Health Condition Monitoring and Fault-Tolerant Operation of Adjustable Speed Drives

Adjustable speed drives (ASDs) have been extensively used in industrial applications over the past few decades because of their benefits of energy saving and control flexibilities. However, the wider penetration of ASD systems into industrial applications is hindered by the lack of health monitoring and fault-tolerant operation techniques, especially in safety-critical applications. In this dissertation, a comprehensive portfolio of health condition monitoring and fault-tolerant operation strategies is developed and implemented for multilevel neutral-point-clamped (NPC) power converters in ASDs. Simulations and experiments show that these techniques can improve power cycling lifetime of power transistors, on-line diagnosis of switch faults, and fault-tolerant capabilities.The first contribution of this dissertation is the development of a lifetime improvement Pulse Width Modulation (PWM) method which can significantly extend the power cycling lifetime of Insulated Gate Bipolar Transistors (IGBTs) in NPC inverters operating at low frequencies. This PWM method is achieved by injecting a zero-sequence signal with a frequency higher than that of the IGBT junction-to-case thermal time constants. This, in turn, lowers IGBT junction temperatures at low output frequencies. Thermal models, simulation and experimental verifications are carried out to confirm the effectiveness of this PWM method. As a second contribution of this dissertation, a novel on-line diagnostic method is developed for electronic switch faults in power converters. Targeted at three-level NPC converters, this diagnostic method can diagnose any IGBT faults by utilizing the information on the dc-bus neutral-point current and switching states. This diagnostic method only requires one additional current sensor for sensing the neutral-point current. Simulation and experimental results verified the efficacy of this diagnostic method.The third contribution consists of the development and implementation of a fault-tolerant topology for T-Type NPC power converters. In this fault-tolerant topology, one additional phase leg is added to the original T-Type NPC converter. In addition to providing a fault-tolerant solution to certain switch faults in the converter, this fault-tolerant topology can share the overload current with the original phase legs, thus increasing the overload capabilities of the power converters. A lab-scale 30-kVA ASD based on this proposed topology is implemented and the experimental results verified its benefits

A Current-Dependent Switching Strategy for Si/SiC Hybrid Switch-Based Power Converters

Abstract: Hybrid switches configured by paralleling Silicon (Si) Insulated Gate Bipolar Transistors (IGBT) and Silicon Carbide (SiC) Metal-Oxide Semiconductor Field-Effect Transistors (MOSFET) have been verified to be a high-efficiency cost-effective device concept. In this paper, a current-dependent switching strategy is introduced and implemented to further improve the performance of Si/SiC hybrid switches. This proposed switching strategy is based on a comprehensive consideration of reducing device losses, reliable operation, and overload capability. Based on the utilization of such Si/SiC hybrid switches and the proposed switching strategy, a 15-kW single-phase H-bridge inverter prototype was implemented and tested in the laboratory. Simulation and experimental results are given to verify the performance of the hybrid switches and the new switching strategy

Efficiency Improvement of Fault-Tolerant Three-Level Power Converters

Fault-tolerant power converters play a critical role in the transportation electrification. However, fault-tolerant operation, high efficiency, and low cost usually result in design criteria that have conflicting constraints and goals. The majority of the fault-tolerant power converter topologies presented in the literature confirm these conflicts. In this paper, three types of fault-tolerant neutral-point clamped (NPC) converters are investigated. Various modulation strategies are explored to reduce the losses of the redundant phase leg. The simulation and experimental results show that the Switching Frequency Optimal Phase opposition Disposition modulation strategy is the most effective approach in minimizing the losses in the redundant phase leg

A Fault-Tolerant T-Type Multilevel Inverter Topology With Increased Overload Capability and Soft-Switching Characteristics

he performance of a novel three-phase four-leg fault-tolerant T-type inverter topology is introduced in this paper. This inverter topology provides a fault-tolerant solution to any open-circuit and certain short-circuit switching faults in the power devices. During any of the fault-tolerant operation modes for these device faults, there is no derating required in the inverter output voltage or output power. In addition, overload capability is increased in this new T-type inverter compared to that in the conventional three-level T-type inverter. Such increase in inverter overload capability is due to the utilization of the redundant leg for overload current sharing with other main phase legs under healthy condition. Moreover, if the redundant phase leg is composed of silicon carbide metal-oxide-semiconductor field-effect transistors, quasi-zero-voltage switching, and zero-current switching of the silicon insulated-gate bipolar transistors (IGBTs) in the conventional main phase legs can be achieved at certain switching states, which can significantly relieve the thermal stress on the outer IGBTs and improve the whole inverter efficiency. Simulation and experimental results are given to verify the efficacy and merits of this high-performance fault-tolerant T-type inverter topology

A Fault-Tolerant T-Type Multilevel Inverter Topology with Soft-Switching Capability Based on Si and SiC Hybrid Phase Legs

The performance of a novel three-phase four-leg fault-tolerant T-Type inverter topology is presented in this paper, which significantly improves the inverter\u27s fault-tolerant capability regarding device switch faults. In this new modular inverter topology, only the redundant leg is composed of Silicon Carbide (SiC) power devices and all other phase legs are constituted by Silicon (Si) devices. The addition of the redundant leg, not only provides fault-tolerant solution to switch faults that could occur in the T-Type inverter, but also can share load current with other phase legs. Moreover, quasi zero-voltage switching (ZVS) and zero-current switching (ZCS) in the Si Insulated-Gate Bipolar Transistors (IGBTs) of the main phase legs can be achieved with the assistance of SiC Metal-Oxide Semiconductor Field-Effect Transistors (MOSFETs) in the redundant leg. Simulation and experimental results are given to verify the efficacy and merits of this high-performance fault-tolerant inverter topology

Centralized Thermal Stress Oriented Dispatch Strategy for Paralleled Grid-Connected Inverters Considering Mission Profiles

One of the major failure causes in the power modules comes from the severe thermal stress in power semiconductor devices. Recently, some local control level methods have been developed to balance the power loss, dealing with the harsh mission profile, in order to reduce the thermal stress. However, there is not any specific system level strategy to leverage these local control level methods responding to the multiple inverters situation. Besides, the impacts of these methods on the thermal cycle and lifetime of the power modules in the long-term time scale have not been evaluated and compared yet. Hence, in this article, a centralized thermal stress oriented dispatch (TSOD) strategy is proposed to take full advantage of these local control level methods, including the switching frequency variation and the reactive power injection, to reduce the thermal stresses for multiple inverters. In addition to the PI controller, the finite control set model predictive control (FCS-MPC) is also explored to synergize with the proposed strategy. The results from the real-time model-in-the-loop testing on a four-paralleled-inverters platform, the reliability assessment, and the experiments all validate the effectiveness of the proposed centralized TSOD strategy on the thermal stress reduction

Cost Minimization of Battery-Supercapacitor Hybrid Energy Storage for Hourly Dispatching Wind-Solar Hybrid Power System

This study demonstrates a dispatching scheme of wind-solar hybrid power system (WSHPS) for a one-hour dispatching period for an entire day utilizing battery and supercapacitor hybrid energy storage subsystem (HESS). A frequency management approach is deployed to extend the longevity of the batteries through extensively utilizing the high energy density property of batteries and the high power density property of supercapacitors in the HESS framework. A low-pass filter (LPF) is employed to decouple the power between a battery and a supercapacitor (SC). The cost optimization of the HESS is computed based on the time constant of the LPF through extensive simulations in MATLAB/SIMULINK platform. The curve fitting and Particle Swarm Optimization approaches are applied to seek the optimum value of the LPF time constant. Several control algorithms as a function of the battery state of charge are developed to achieve accurate estimation of the grid reference power for each one-hour dispatching period. This estimation helps to minimize the energy storage cost, in addition to ensuring that the HESS has sufficient capacity for next-day operation. The optimum value of depth of discharge for HESS considering both cycling and calendar expenses has also been investigated for the best competitive energy storage cost for hourly dispatching the power of the WSHPS. This research also presents an economic comparison to investigate the significance of using different types of energy storage for hourly dispatching the WSHPS. The simulation results show that the presented HESS is superior to battery or SC-only operation